Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s

Mots clés : Code correcteur d'erreurs, Turbocodes en blocs, Décodage entièrement parallèle, Architecture à très haut débit. Abstract This paper presents a new circuit architecture for turbo decoding, which achieves ultra high data rates when using product codes as error correcting codes. This architecture is able to decode product codes using binary BCH or m-ary Reed Solomon component codes. The major advantage of our full-parallel architecture is that it enables the memory block between each half-iteration to be removed. In fact, the proposed architecture opens the way to numerous applications such as optical transmission. In particular, our block turbo decoding architecture can support optical transmission at data rates above Gbit/s. Architecture de turbo décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s